C. Pan and A. Naeemi, “Non-Boolean Computing Benchmarking for beyond-CMOS Devices based on Cellular Neural Network,” IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), vol. 2, pp. 36-43, December, 2016.

R. Nashed, C. Pan, K. Brenner, and A. Naeemi, "Ultra-High Mobility in Dielectrically Pinned CVD Graphene". IEEE Journal of the Electron Devices Society, 4(6), pp. 466-472, Nov 2016.

N. Kani, S. Rakheja, and A. Naeemi. "A Probability-Density Function Approach to Capture the Stochastic Dynamics of the Nanomagnet and Impact on Circuit Performance." IEEE Trans. Electron Devices, vol.10, pp. 4119-4126, Oct. 2016.

C. Pan and A. Naeemi, “A Proposal for Energy-Efficient Cellular Neural Network Based on Spintronic Devices,” IEEE Trans. Nanotechnology (TNANO), vol. 15, pp. 820-827, August 2016.

V. Kumar, H. Oh, X. Zhang, L. Zheng, M.S. Bakir, A. Naeemi, “Impact of on-chip interconnect on the performance of 3D integrated circuits with through Silicon Vias: Part I,” IEEE Trans. Electron Devices, vol. 63, pp. 2503 – 2509, May 2016.

X. Zhang, V. Kumar, H. Oh, L. Zheng, G.S. May, A. Naeemi, M. Bakir, “Impact of on-chip interconnect on the performance of 3D integrated circuits with through silicon vias: Part II,” IEEE Trans. Electron Devices, vol. 63, pp. 2510 – 2516, May 2016.

H. Aghasi, R. M. Iraei, A. Naeemi, and E. Afshari, “Smart detector cell: A scalable all-spin circuit for low power non-Boolean pattern recognition,” IEEE Trans. on Nanotechnology, vol. 15, pp. 356-366, May 2016 (Featured on the cover page).

C. Pan and A. Naeemi, “Interconnect design and benchmarking for charge-based beyond-CMOS device proposals,” IEEE Electron Device Letters, vol. 37, pp. 508-511, April 2016.

N. Kani, S. Chang, S. Dutta, and A. Naeemi, “A model study of an error-free magnetization reversal through dipolar coupling in a two-magnet system,” IEEE Trans. Magnetics, vol.52, no.2, pp.1-12, Feb. 2016 (Featured on the cover page).

S. -C. Chang, N. Kani, S. Manipatruni, D. E. Nikonov, I. A. Young, and A. Naeemi, “Scaling limits on all-spin logic,” IEEE Trans. on Magnetics, vol. 52, no. 7, 3400404, 2016.

S. Dutta, D. E. Nikonov, S. Manipatruni, I. A. Young, A Naeemi, "Phase-dependent deterministic switching of magnetoelectric spin wave detector in the presence of thermal noise via compensation of demagnetization", Applied Physics Letters 107.19 (2015): 192404.

S. Chang, S. Dutta, S. Manipatruni, D. E. Nikonov, I. A. Young, A. Naeemi, A., "Interconnects for All-Spin Logic Using Automotion of Domain Walls," in Exploratory Solid-State Computational Devices and Circuits, IEEE Journal on , vol.1, no., pp.49-57, Dec. 2015.

D. Prasad, A. Ceyhan, C. Pan, and A. Naeemi, “Adapting interconnect technology to multigate transistors for optimum performance,” IEEE Trans. Electron Devices, vol.62, no.12, pp. 3938-3944, 2015.

S. Dutta, D. E. Nikonov, S. Manipatruni, I. A. Young, A Naeemi, "Compact Physical Model for Crosstalk in Spin-Wave Interconnects," in Electron Devices, IEEE Transactions on , vol.62, no.11, pp.3863-3869, Nov. 2015.

S. Dutta, S. -C. Chang, N. Kani, D. E. Nikonov, S. Manipatruni, I. A. Young, and A. Naeemi, “Non-volatile Clocked Spin Wave Interconnect for Beyond-CMOS Nanomagnet Pipelines”, Nature Scientific Reports, 5, 2015.

C. Pan, P. Raghavan, A. Ceyhan, F. Catthoor, Z. Tokei, and A. Naeemi, “Technology/circuit/system co-optimization and benchmarking for multilayer graphene interconnects at sub-10nm technology Nodes,” IEEE Trans. Electron Devices, vol. 62, pp. 2071-2077, May 2015.

C. Pan and A. Naeemi, “A paradigm shift in local interconnect technology design in the era of nanoscale multi-gate and gate-all-around devices,” IEEE Electron Dev. Lett., vol. 36, pp. 274-276, March 2015.

C. Pan and A. Naeemi, “A fast system-level design methodology for heterogeneous multi-core processors using emerging technologies,” to be published in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, March, 2015.

A.Ceyhan, M. Jung, S. Panth, S.K. Lim and A. Naeemi “Evaluating Chip-level Impact of Cu. low-k Performance Degradation on Circuit Performance at Future Technology Nodes,” IEEE Trans. Electron Devices, vol. PP, no.99, pp.1, Feb. 2015.

C. Pan, R. Baert, I. Ciofi, Z. Tokei, and A. Naeemi, “System-level variation analysis for interconnection networks at sub-10nm technology nodes,” IEEE Trans. Electron Devices, submitted, Jan. 2015.

S. Dutta, D. E. Nikonov, S. Manipatruni, I. A. Young, and A. Naeemi, “ SPICE circuit modeling of PMA spin wave bus excited using magnetoelectric effect,” IEEE Trans. Magnetics, vol.50, no.9, pp.1,11, Sep. 2014.

S. -C. Chang, S. Manipatruni, D. E. Nikonov, I. A. Young, and A. Naeemi, “Design and Analysis of Si Interconnects for All-spin Logic,” IEEE Trans. Magnetics, Sep. 2014.

S. -C. Chang, R. Mousavi, S. Manipatruni, D. E. Nikonov, I. A. Young, and A. Naeemi, ”Design and Analysis of Copper and Aluminum Interconnects for All-spin Logic,” IEEE Trans. Electron Devices, vol. 61, no. 8, pp. 2905–2911, Aug. 2014.

V. Kumar, R. Sharma, E. Uzunlar, Li Zheng, R. Bashirullah, P. Kohl, M. Bakir, and A. Naeemi, “Airgap interconnects: modeling, optimization, and benchmarking for backplane, PCB, and interposer applications,” IEEE Trans. Components, Packaging, and Manufacturing Technology, vol. 4, pp.1335-1346, Aug. 2014.

P. Bonhomme, S. Manipatruni, R. Mousavi, S. Rakheja, S. -C. Chang, D. E. Nikonov, I. A. Young, and A. Naeemi, “Circuit Simulation of Magnetization Dynamics and Spin Transport, IEEE Trans. Electron Devices, vol. 61, pp. 1553-1560, May 2014.

C. Pan and Azad Naeemi, “A Proposal for a novel hybrid interconnect technology for the end of roadmap,” IEEE Electron Device Lett., vol. 35, pp. 250-252, Jan. 2014.

C. Pan and Azad Naeemi, “A paradigm shift in local interconnect technology design in the era of nanoscale multi-gate and gate-all-around devices,” IEEE Electron Device Lett., Jan. 2014.

A. Ceyhan and A. Naeemi, “Cu/Low- k Interconnect Technology Design and Benchmarking for Future Technology Nodes,” IEEE Trans. Electron Devices, vol. 60, pp. 4041-4047, Dec. 2013.

S. Rakheja, S. -C. Chang, and A. Naeemi, “Impact of Dimensional Scaling and Size Effects on Spin Transport in Copper and Aluminum Interconnects, IEEE Trans. Electron Devices, vol. 60, pp. 3013-3939, Nov. 2013.

S. Rakheja and A. Naeemi, “Roles of Doping, Temperature, and Electric Field on Spin Transport Through Semiconducting Channels in Spin Valves,” IEEE Trans. Nanotechnology, vol. 12, pp. 796-805, Sept. 2013.

S. Rakheja, V. Kumar, and A. Naeemi, “Applications of graphene nanoribbons as on-chip interconnects,” Proc. IEEE, vol. 101, pp. 1740 – 1765, July 2013 (Invited).

P. Zheng, S. E. Brian, Y. Yang, R. Murali, A. Naeemi, and J. D. Meindl, “Hydrogenation of Graphene Nanoribbon Edges: Improvement in Carrier Transport,” IEEE Electron Device Lett., vol. 34, pp. 707-709, May 2013.

A. Ceyhan and A. Naeemi, “Cu interconnect limitations and opportunities for SWNT interconnects at the end of the roadmap,” IEEE Trans. Electron Devices, vol. 60, pp. 374–382, Jan. 2013.

V. Kumar, S. Rakheja and A. Naeemi, “Performance and energy-per-bit modeling of multi-layer graphene nanoribbon conductors,” IEEE Trans. Electron Devices, vol. 59, pp. 2753-2761, October 2012.

G. Huang ; M.S. Bakir, A. Naeemi, J. D. Meindl, “Power Delivery for 3-D Chip Stacks: Physical Modeling and Design Implication,” IEEE Trans. Components, Packaging and Manufacturing Technology, vol. 2, pp. 852-859, May 2012.

S. Rakheja and A. Naeemi, “Graphene nanoribbon spin interconnects for non-local spin-torque circuits: Comparison of performance and energy-per-bit with CMOS interconnects,” IEEE Trans. Electron Devices, vol. 59, pp. 51-59, Jan. 2012.

A. Balakrishnan and A. Naeemi, “Interconnect network analysis of many-core chips,” IEEE Trans. Electron Devices, vol. 58, pp. 2831-2837, Sept. 2011.

S. Rakheja and A. Naeemi, "Modeling interconnects for post-CMOS devices and comparison with copper interconnects," IEEE Trans. Electron Devices, vol. 58, pp. 1319-1328, May 2011.

O. Jamal and A. Naeemi, “Ultra-low power single-wall carbon nanotube interconnects for subthreshold circuits,” IEEE Trans. Nanotechnology, vol. 10, pp. 99-101, Jan. 2011.

S. Rakheja and A. Naeemi, “Interconnects for novel state variables: performance modeling and device and circuit implications,” IEEE Trans. Electron Devices, vol. 57, pp. 2711-2718, Oct. 2010.

A. Balakrishnan and A. Naeemi, “Optimal global interconnects for networks-on-chip in many core architectures,” IEEE Electron Device Letters, vol. 31, pp. 290-292, April 2010.

A. Naeemi and J. D. Meindl, "Compact physics-based circuit models for graphene nanoribbon interconnects," IEEE Trans. Electron Devices, vol.56, pp. 1822-1833, Sept. 2009 (Invited).

A. Naeemi and J. D. Meindl, “Performance modeling for single- and multi-wall carbon nanotubes as signal and power interconnects in gigascale systems,” IEEE Trans. Electron Devices, vol. 55, pp. 2574-2582, Oct. 2008.

A. Naeemi and J. D. Meindl, “Electron transport modeling for junctions of zigzag and armchair graphene nanoribbons,” IEEE Electron Device Letters, vol. 29, pp. 497–99, May 2008.

A. Naeemi and J. D. Meindl, “Conductance modeling for graphene nanoribbon (GNR) interconnects,” IEEE Electron Device Letters, vol. 28, pp. 428–431, May 2007.

A. Naeemi and J. D. Meindl, “Physical modeling for temperature coefficient of resistance of carbon nanotubes,” IEEE Electron Device Letters, vol. 28, pp. 135–138, Feb. 2007.

A. Naeemi and J. D. Meindl, “Design and performance modeling for single-wall carbon nanotubes as local, semi-global, and global interconnects in gigascale integrated systems,” IEEE Trans. Electron Devices, vol. 54, pp. 26–37, January 2007.

A. Naeemi and J. D. Meindl, “Compact physical models for multiwall carbon-nanotube interconnects,” IEEE Electron Device Letters, vol. 27, pp. 338–340, May 2006.

A. Naeemi and J. D. Meindl, “Mono-layer metallic nanotube interconnects: promising candidates for short local interconnects,” IEEE Electron Device Letters, vol. 26, pp. 544–546, Aug. 2005.

V. Mulé, R. Villalaz, J. P. Jayachandran, A. Naeemi, P. A. Kohl, T. K. Gaylord, and J. D. Meindl, “Polylithic integration of electrical and optical interconnect technologies for CMOS GSI,” IEEE Trans. Advanced Packaging, vol. 28, pp. 421–433, Aug. 2005.

A. Naeemi and J. D. Meindl, “Impact of electron-phonon scattering on the performance of carbon nanotube interconnects for gigascale integration (GSI),” IEEE Electron Device Letters, vol. 26, pp. 476–478, July 2005.

A. Naeemi, R. Sarvari, and J. D. Meindl, “Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI),” IEEE Electron Device Letters, vol. 26, pp. 84–86, Feb. 2005.

A. Naeemi, J. A. Davis, and J. D. Meindl, “Compact physical models for multilevel interconnect crosstalk in gigascale integration (GSI),” IEEE Trans. Electron Devices, vol. 51, pp. 1902–1912, Nov. 2004.

A. Naeemi, J. A. Davis, and J. D. Meindl, “Analysis and optimization of co-planar RLC lines for GSI global interconnection,” IEEE Trans. Electron Devices, vol. 51, pp. 985–994, June 2004.

A. Naeemi, J. Xu, A. V. Mulé, T. K. Gaylord, and J. D. Meindl, “Optical and electrical interconnect partition length based on chip-to-chip bandwidth maximization,” IEEE Photonics Technology Letters, vol. 16, pp. 1221–1223, April 2004.

A. Naeemi, R. Venkatesan, and J. D. Meindl, “Optimal global interconnects for GSI,”IEEE Trans. Electron Devices, vol. 50, pp. 980–987, April 2003.