Microelectronics Research Center
791 Atlantic Drive, Room 261
Atlanta, Georgia 30332
Professor Naeemi received his B.S. degree in electrical engineering from Sharif University, Tehran, Iran in 1994, and his M.S. and Ph.D. degrees in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, Ga. in 2001 and 2003, respectively.
Dr. Naeemi's research crosses the boundaries of materials, devices, circuits, and systems investigating integrated circuits based on conventional and emerging nanoelectronic and spintronic devices and interconnects. He serves as the leader of the beyond-CMOS benchmarking research at the Semiconductor Research Corporation (SRC) Nanoelectronics Research Initiative (NRI) and the Semiconductor Technology Advanced Research Network (STARnet). He is the recipient of the IEEE Electron Devices Society (EDS) Paul Rappaport Award for the best paper that appeared in IEEE Transactions on Electron Devices during 2007. He has received an NSF CAREER Award, an SRC Inventor Recognition Award, and several best paper awards at international conferences. Professor Naeemi is also the recipient of 2014 Richard M. Bass/Eta Kappa Nu Outstanding Teacher Award selected by the vote of the ECE senior class and the 2014 ECE Outstanding Junior Faculty Member Award.
Chenyun Pan was born in Shanghai, China in 1988. He received a Bachelor of Science in Microelectronics from Shanghai Jiaotong Univerity in 2010. In Spring 2011, he joined Nanoelectronics Research Lab as a PhD student and received his PhD in Fall 2015. In Summer 2014 and Spring 2015, he worked in IMEC, Belgium, as a visiting scholar, and conducted research on circuit- and system-level benchmarking and optimization for multilayer graphene interconnects and vertical and lateral gate-all-around FETs. His research focuses on the device and interconnect modeling, and the system-level benchmarking and performance optimization for various emerging beyond-CMOS technologies.
Thesis Title: Performance modeling for emerging interconnects in multicore chips
Thesis Title: Interconnects for Future Technology Generations-Conventional CMOS with Copper/low–κ and Beyond
Thesis Title: Circuit and architecture implications of post-CMOS devices
Thesis Title: Ultra Low-Power Interconnects for Subthreshold Circuits
Thesis Title: Edge Passivation for Graphene Nanoribbons
Thesis Title: Circuit Modeling of Spintronic Devices: A SPICE Implementation
Thesis Title: Interconnects for Post-CMOS Non-Charge Based Switching Devices
Intel PhD Fellowship for 2011-2012 Academic Year
Thesis Title: Design and Optimization for Chip-to-Chip Interconnect