Book Chapters

S. Rakheja, A. Ceyhan, and A. Naeemi, “Interconnect considerations,” in CMOS and Beyond: Logic Switches for Terascale Integrated Circuits, K. Kuhn & T. J. K. Liu (Eds.), Cambridge University Press 2014.

S. Rakheja and A. Naeemi, “Communicating Novel Computational State Variables: Post-CMOS Logic,” IEEE Nanotechnology Magazine, vol. 7, pp. 15-23, March 2013.

S. Rakheja and A. Naeemi, “On physical limits and challenges of graphene nanoribbons as interconnects for all-spin logic,” in Nanoelectronic Device Applications Handbook, J. Morris & K. Iniewski (Eds.), CRC Press 2012.

S. Rakheja and A. Naeemi, “Interconnects for alternative state variables,” in Graphene Nanoelectronics, R. Murali (Ed.), Springer, 2011.

A. Naeemi and J. D. Meindl, “Carbon nanotube interconnect modeling,” in Carbon Nanotube Electronics, J. Kong and A. Javey (Eds.), Springer 2009.

A. Naeemi and J. D. Meindl, “Carbon nanotube interconnects,” Annual Review of Materials Research, Keynote Topic on “Materials after CMOS,” pp. 255-275, Jan. 2009.

G. Huang, K. Shakeri, A. Naeemi, M. Bakir, and J. Meindl, “On-chip power supply noise modeling and chip/package co-design of gigascale and 3D integrations,” in Interconnect Technologies for 3D Integrated Systems, M. Bakir and J. Meindl (Eds.), Artech House 2008.

A. Naeemi and J. D. Meindl, “Carbon nanotube interconnects,” in NanoTechnology: An Open Text, S. Campbell (Ed.), National Science Foundation (NSF) National Nanotechnology Infrastructure Network (NNIN) 2007.

J. A. Davis, A. Naeemi, and J. D. Meindl, “Distributed RC and RLC models,” in Interconnect Technology and Design for Gigascale Integration, J. A. Davis and J. D. Meindl (Eds.), Kluwer, 2003.