Conference Papers

[ 2015 ]

J. Mohseni, C. Pan, and A. Naeemi, “Performance modeling and optimization for on-chip interconnects in memory arrays”, IEEE Int. Electrical Performance of Electronic Packages and Systems Conference (EPEPS), San Jose, CA, October 2015, pp. 149-152.

C. Pan and A. Naeemi, “A fast system-level design methodology for heterogeneous multi-core processors using emerging technologies,” Proc. SRC TECHCON, Austin, TX, September 2015, pp. 1-4.

C. Pan and A. Naeemi, “A paradigm shift in local interconnect technology design in the era of nanoscale multi-gate and gate-all-around devices,” Proc. SRC TECHCON, Austin, TX, September 2015, pp. 1-4.

Rose Peng, Mithila Tople, Bill Dorn, Azad Naeemi, Nassim JafariNaimi, “A novel interactive paradigm for teaching quantum mechanics,” in 11th annual Games+Learning+Society Conference (GLS11), Madison, WI, July 2015, pp. 1-6.

N. Kani, S. Dutta, A. Naeemi, "Analysis of coupling strength in multi-domain magneto-systems," in Device Research Conference (DRC), 2015 73rd Annual , vol., no., pp.111-112, 21-24 June 2015.

C. Pan, P. Raghavan, F. Catthoor, Z. Tokei, and A. Naeemi, “Technology/circuit co-optimization and benchmarking for multilayer graphene interconnects at sub-10nm technology node,” IEEE Int. Symp. Quality Electronic Design (ISQED), Santa Clara, CA, March 2015, pp. 1-5.

[ 2014 ]

C. Pan, and A. Naeemi, “System-level chip/package co-design for multi-core processors implemented with power-gating technique,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), Portland, OR, Oct. 2014, pp. 1-4.

A. Ceyhan, M. Jung, S. Panth, S.K. Lim and A. Naeemi, “Impact of Size Effects in Local Interconnects for Future Technology Nodes: A Study Based on Full-chip Layouts,” Semiconductor Research Corporation TECHCON, Austin, TX., Sep. 2014, pp. 1-4.

C. Pan, and A. Naeemi, and A. Ghosh, “A proposal for a novel aluminum-copper hybrid interconnect technology for the end of roadmap,” Semiconductor Research Corporation TECHCON, Austin, TX., Sep. 2014, pp. 1-4.

V. Kumar, R. Alapati, M. Bakir, A. Naeemi, “Impact of on-chip interconnects on the Performance of 3D ICs”, Semiconductor Research Corporation TECHCON, Austin, TX., Sep. 2014, pp. 1-4.

Kani, Nickvash, and Azad Naeemi. "Wiring resource minimization for physically-complex Network-on-Chip architectures." System-on-Chip Conference (SOCC), 2014 27th IEEE International. IEEE, Las Vegas, Nevada, Sept. 2014.

V. Kumar, R. Nashed, K. Brenner, R. Sandhu, A. Naeemi, “System Level Analysis and Benchmarking of Graphene Interconnects for Low-Power Applications”, IEEE Int. Symp. Electromagnetic Compatibility, Raleigh, NC, Aug. 2014, pp. 1-6 (Invited).

N. Kani, and Azad Naeemi. "Pipeline design in spintronic circuits." Nanoscale Architectures (NANOARCH), 2014 IEEE/ACM International Symposium on. IEEE, Paris, France, July 2014.

A. Ceyhan, M. Jung, S. Panth, S.K. Lim and A. Naeemi, “Impact of Size Effects in Local Interconnects for Future Technology Nodes: A Study Based on Full-chip Layouts,” IEEE Interconnect Technology Conf., June 2014, pp. 345-348.

S. -C. Chang, A. Ceyhan, V. Kumar, A. Naeemi, “Performance Modeling for Emerging Interconnect Technologies in CMOS and Beyond-CMOS Circuits,” International Symposium on Low Power Electronics and Design (ISLPED’14), pp. 63–68, June 2014 (Invited Paper).

A. Naeemi, C. Pan, A. Ceyhan, R. M. Iraei, V. Kumar, Sh. Rakheja, "BEOL scaling limits and next generation technology prospects," ACM/EDAC/IEEE Design Automation Conference (DAC), pp.1-6, 1-5 June 2014 (Invited Paper).

Iraei, R. M., Bonhomme, P., Kani, N., Manipatruni, S., Nikonov, D. E., Young, I. A., & Naeemi, A., “Impact of dimensional scaling and size effects on beyond CMOS All-Spin Logic interconnects,” IEEE Int. Interconnect Technology Conf., San Jose, CA., May 2014, pp. 353-356.

C. Pan and A. Naeemi, “System-level variation analysis for interconnection networks,” IEEE Int. Interconnect Technology Conf., San Jose, CA., May 2014, pp. 303-306.

C. Pan, S. Mukhopadhyay, and A. Naeemi, “An analytical approach to system-level variation analysis and optimization for multi-core processors,” IEEE Int. Symp. Quality Electronic Design (ISQED), Santa Clara, CA, March 2014, pp. 99-106.

[ 2013 ]

A. Ceyhan and A. Naeemi, “Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices,” Semiconductor Research Corporation TECHCON, Austin, TX., Sept. 2013, pp. 1-4.

R. Sajjad, C. Pan, A. Naeemi, and A. Ghosh, “Novel switching mechanism with graphene pn junctions: device physics and circuit analysis,” Semiconductor Research Corporation TECHCON, Austin, TX., Sept. 2013, pp. 1-4.

V. Kumar, S. Rakheja, and A. Naeemi, “Review of multi-layer graphene nanoribbons for on-chip interconnect applications,” IEEE Int. Symp. Electromagnetic Compatibility, Denver, CO, Aug. 2013, pp. 528-533. (Invited Paper).

S. Rakheja, V. Kumar, and A. Naeemi, “Performance modeling for interconnects for conventional and emerging switches,” ACM/IEEE Int. Workshop on System Level Interconnect Prediction (SLIP), Austin, TX, June 2013, pp. 1-9 (Invited).

C. Pan, and A. Naeemi, “System-level analysis for 3D interconnection networks,” IEEE Interconnect Technology Conf., Kyoto, Japan, June 2013, pp. 1-3.

V. Kumar, Zh. Li, M. Bakir, and A. Naeemi, “Compact modeling and optimization of fine-pitch interconnects for silicon interposers,” IEEE Interconnect Technology Conf., Kyoto, Japan, June 2013, pp. 1-3.

E. Uzunlar, R. Sharma, R. Saha, V. Kumar, R. Bashirullah, A. Naeemi, and P. Kohl, “Design and fabrication of ultra low-loss, high-performance 3D chip-chip air-clad interconnect pathway,” IEEE Electronic Components and Technology Conference (ECTC), Las Vegas, NV, May 2013, pp. 1425 – 1432.

C. Pan, A. Ceyhan, and A. Naeemi, “System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs,” IEEE Int. Symp. Quality Electronic Design (ISQED), Santa Clara, CA, March 2013, pp. 196-202.

A. Ceyhan and A. Naeemi, “Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices,” IEEE Int. Symp. Quality Electronic Design (ISQED), Santa Clara, CA, March 2013, pp. 203-209.

[ 2012 ]

C. Pan, and A. Naeemi, “System-Level Performance Optimization and Benchmarking for On-Chip Graphene Interconnects,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), Tempe, AZ, Oct. 2012, pp. 33-36.

V. Kumar, S. Rakheja, and A. Naeemi, “Graphene Nanoribbon Interconnects,” Advanced Metallization Conference, Tokyo, Japan, Oct. 2012, pp. 118-119 (Invited Paper).

R. Sharma, E. Uzunlar, V. Kumar, R. Bashirullah, A. Naeemi, and P. Kohl, “Design and fabrication of air-clad TSVs in silicon interposer,” Semiconductor Research Corporation TECHCON, Austin, TX., Sept. 2012, pp. 1-4.

C. Pan and A. Naeemi, “Device-level modeling and system-level optimization for graphene PN junction device,” Semiconductor Research Corporation TECHCON, Austin, TX., Sept. 2012, pp. 1-4.

S. Rakheja and A. Naeemi, “Graphene nanoribbons for all-spin logic: effects of dimensional scaling on spin transport,” Semiconductor Research Corporation TECHCON, Austin, TX., Sept. 2012, pp. 1-4 (Best in Session Award).

S. Rakheja and A. Naeemi, “Compact modeling of spin-transport parameters in semiconducting channels in non-local spin-torque devices,” IEEE NANO, Birmingham, UK, Aug. 2012, pp. 1-6.

V. Kumar and A. Naeemi, “Analytical models for the frequency response of multi-layer graphene nanoribbon interconnects,” IEEE Int. Symp. Electromagnetic Compatibility, Pittsburgh, PA, Aug. 2012, pp. 440-445. (Invited Special Session Paper).

N. Kani and A. Naeemi, “Circuit-technology co-optimization of heterogeneous hierarchical network-on-chips,” IEEE Int. Interconnect Technology Conf., San Jose, CA., June 2012, pp. 1-3.

V. Kumar, R. Sharma, J. Chen, A. Kapoor, R. Bashirullah, P. Kohl and A. Naeemi, “Compact modeling and performance optimization of 3D chip-to-chip interconnect with transmission lines, vias and discontinuities,” IEEE Int. Interconnect Technology Conf., San Jose, CA., June 2012, pp. 1-3.

A. Ceyhan and A. Naeemi, “System-level design and performance modeling for multilevel interconnect networks for carbon nanotube field-effect transistors,” IEEE International Conference on IC Design and Technology (ICICDT), Austin, TX, May 2012, pp. 1-6.

R. Sharma, E. Uzunlar, V. Kumar, R. Saha, X. Yeow, R. Bashirullah, A. Naeemi and P. Kohl, “Design and Fabrication of Low-loss Horizontal and Vertical Interconnect links using Air-Clad Transmission Lines and Through Silicon Vias”, IEEE Electronic Components Technology Conference, San Diego, CA, May 2012, pp. 1-8.

C. Pan and A. Naeemi, “System-level optimization and benchmarking of graphene pn junction logic system based on empirical CPI model,” IEEE International Conference on IC Design and Technology (ICICDT), Austin, TX, May 2012, pp. 1-6 (Best Student Paper Award).

C. Pan and A. Naeemi, “Device- and system-level performance modeling for graphene p-n junction logic” IEEE Int. Symp. Quality Electronic Design (ISQED), Santa Clara, CA, March 2012, pp. 1-6 (Best Paper Award).

S. Rakheja and A. Naeemi, “Interconnect analysis in spin-torque devices: performance modeling, optimal repeater insertion, and circuit-size limits,” IEEE Int. Symp. Quality Electronic Design (ISQED), Santa Clara, CA, March 2012, pp. 1-6.

[ 2011 ]

A. Ceyhan and A. Naeemi, “Multilevel interconnect networks for the end of the roadmap: conventional Cu/low-k and emerging carbon based interconnects,” Semiconductor Research Corporation TECHCON, Austin, TX., Sept. 2011, pp. 1-4.

V. Kumar and A. Naeemi, “Modeling and optimization of multi-layer graphene nanoribbon interconnects,” Semiconductor Research Corporation TECHCON, Austin, TX., Sept. 2011, pp. 1-4.

S. Rakheja and A. Naeemi, “Interconnects for novel state variables: modeling physical limits and comparison with CMOS,” Semiconductor Research Corporation TECHCON, Austin, TX., Sept. 2011, pp. 1-4.

S. Rakheja and A. Naeemi “On Physical limits and challenges of interconnects for spin devices”, IEEE NANO, Portland, OR, Aug. 2011, pp. 1-6.

A. Ceyhan and A. Naeemi, “Multilevel interconnect networks for the end of the roadmap: conventional Cu/low-k and emerging carbon based interconnects,” IEEE Interconnect Technology Conf., Dresden, Germany, May 2011, pp. 1-3.

V. Kumar, S. Rakheja and A. Naeemi, “Modeling and optimization for multi-layer graphene nanoribbon conductors,” IEEE Interconnect Technology Conf., Dresden, Germany, May 2011, pp. 1-3.

A. Banerjee, S. Chatterjee, A. Naeemi and A. Chatterjee, “Power aware post-manufacture tuning of analog nanocircuits,” IEEE European Test Symposium, Trondheim, Norway, May 2011, pp. 57-62.

V. Kumar, R. Bashirullah, and A. Naeemi, “Modeling, optimization and benchmarking of chip-to-chip electrical interconnects with low loss air-clad dielectrics,” Proc. IEEE Electronic Components and Technology Conf., May 2011, pp. 2084-2090.

S. Rakheja and A. Naeemi, “Performance, energy-per-bit, and circuit size limits of post-CMOS logic circuits- modeling, analysis and comparison with CMOS logic,” IEEE Interconnect Technology Conf., Dresden, Germany, May 2011, pp. 1-3 (Invited).

S. Rakheja and A. Naeemi, “Interconnection Aspects of Spin Torque Devices: Delay, Energy-Per-Bit, and Circuit Size Modeling,” IEEE Int. Symp. Quality Electronics Design, March 2011, Santa Clara, CA, pp. 1-9.

[ 2010 ]

A. Naeemi, “Work In Progress - Carbon nanomaterials: a platform to teach fundamentals of nanoelectronics,” 40th ASEE/IEEE Frontiers in Education Conference, Washington, DC, Oct. 2010, pp. 1-2.

S. Rakheja, A. Naeemi, and J. D. Meindl, “Physical limitations on delay and energy dissipation of interconnects for post-CMOS devices,” IEEE Int. Interconnect Technology Conf., June 2010, pp. 1-3.

O. Jamal and A. Naeemi, “Evolutionary and revolutionary interconnect technologies for performance enhancement of subthreshold circuits,” IEEE Int. Interconnect Technology Conf., June 2010, pp. 1-3.

A. Balakrishnan and A. Naeemi, “Bandwidth, delay and energy aware optimization of global interconnects for many-core architectures,” IEEE Int. Interconnect Technology Conf., June 2010, pp. 1-3.

J. D. Meindl, A. Naeemi, M. Bakir, and R. Murali, “Nanoelectronics in retrospect, prospect and principle,” IEEE Intl. Solid State Circuits Conf., Feb. 2010 (Invited Plenary Paper), pp. 31-35.

[ 2009 ]

A. Balakrishnan and A. Naeemi, “Optimal global interconnects for networks-on-chip in many core architectures,” Semiconductor Research Corporation TECHCON, Sept. 14, 2009, pp. 1-4.

[ 2008 ]

A. Naeemi and J. D. Meindl, “Physical models for electron transport in graphene nanoribbons and their junctions,” Embedded Workshop in IEEE. Intl. Conf. Computer Aided Design, Nov. 2008, pp. 400-405 (Invited).

M. S. Bakir, C. King, D. Sekar, H. Thacker, B. Dang, G. Huang, A. Naeemi, and J. D. Meindl, “3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation,” IEEE Custom Integrated Circuit Conf., Sept. 2008, pp. 663-670.

A. Naeemi and J. D. Meindl, “Performance benchmarking for graphene nanoribbon, carbon nanotube, and Cu interconnects,” IEEE Intl. Interconnect Technology Conf, June 2008, pp. 183-185 (Invited).

G. Huang, A. Naeemi, T. Zhou, D. O'Connor, B. Singh, A. Muszynski, W. D. Becker, J. Venuto, and J. D. Meindl, "Compact physical models of chip and package power and ground distribution networks for gigascale integration," IEEE Electronic Components and Technology Conference, Orlando, May 2008, pp. 641-645.

[ 2007 ]

D. C. Sekar, A. Naeemi, R. Sarvari, J. D. Davis, J. D. Meindl, “Intsim: a CAD tool for optimization of multilevel interconnect networks,” IEEE/ACM Int. Conf. Computer Aided Design, Nov. 2007, pp. 560-567.

G. Huang, M. S. Bakir, A. Naeemi, H. Chen, and J. D. Meindl, “Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication,” IEEE Electrical Performance of Electronic Packaging, Oct. 2007, pp. 205-208.

G. Huang, D. Sekar, A. Naeemi, K. Shakeri, and J. D. Meindl, “Physical model for power supply noise and chip/package co-design in gigascale systems with the consideration of hot spots,” IEEE Custom Integrated Circuits Conf., Sept. 2007, pp. 841-844.

A. Naeemi, R. Sarvari, and J. D. Meindl, “Performance modeling and optimization for single and multi-wall carbon nanotube interconnects,” ACM Design Automation Conf., San Diego, CA, June 2007, pp. 568-573 (special session paper).

R. Sarvari, A. Naeemi, P. Zarkesh-Ha, and J. D. Meindl, “Design and optimization for nanoscale power distribution networks in gigascale systems,” IEEE Int. Interconnect Technology Conf., June 2007, pp. 190-192.

A. Naeemi and J. D. Meindl, “Carbon nanotube interconnects,” ACM Int. Symp. on Physical Design, May 2007, pp. 77-84 (Invited).

A. Naeemi, G. Huang, J. D. Meindl, “Performance modeling for carbon nanotube interconnects in on-chip power distribution,” IEEE Int. Electronic Components and Tech. Conf., May 2007, pp. 420-428.

G. Huang, D. Sekar, A. Naeemi, K. Shakeri, and J. D. Meindl, “Compact physical models for power supply noise and chip/package co-design of gigascale integration,” IEEE Int. Electronic Components and Tech. Conf., May 2007, pp. 1659-1665.

[ 2006 ]

A. Naeemi and M. S. Bakir, “Chip-level and Input/Output Interconnects for Gigascale SOCs: Limits and Opportunities,” IEEE SoC Conf., Sept. 2006, pp. 323-324.

A. Naeemi, R. Sarvari, and J. D. Meindl, “On-chip interconnect networks at the end of the roadmap: limits and nanotechnology opportunities,” IEEE Int. Interconnect Technology Conf., June 2006, pp. 221-223 (Invited paper).

[ 2005 ]

G. Huang, A. Naeemi, and J. D. Meindl, “Minimizing energy-per-bit for on-board LC transmission lines,” IEEE Int. Interconnect Technology Conf., June 2005, pp. 77-79.

A. Naeemi and J. D. Meindl, “Impact of deep sub-ambient cooling on GSI interconnect performance,” IEEE Int. Interconnect Technology Conf., June 2005, pp. 156-158.

R. Sarvari, A. Naeemi, and J. D. Meindl, “Impact of size effects on the resistivity of copper wires and consequently the design and performance of metal interconnect networks,” IEEE Intl. Interconnect Technology Conf, June 2005, pp. 197-199.

A. Naeemi, Y. Joshi, A. Federov, P. Kohl, J. D. Meindl, “The urgency of deep sub-ambient cooling for gigascale integration,” IEEE Integrated Circuit Design and Technology, May 2005, pp. 171-175.

[ 2004 ]

A. Naeemi, R. Sarvari, and J. D. Meindl, “Performance comparison between carbon nanotube and copper interconnects for GSI,” IEEE Int. Electron Device Meeting, Dec. 2004, pp. 699-702.

A. Naeemi and J. D. Meindl, “An upper limit for aggregate I/O interconnect bandwidth of GSI chips constrained by power dissipation,” IEEE Int. Interconnect Technology Conf., June 2004, pp. 157-159.

R. Sarvari, A. Naeemi, and J. D. Meindl, “General compact model for bit-rate limit of electrical interconnects considering DC resistance, skin effect, and surface scattering,” IEEE Intl. Interconnect Technology Conf., June 2004, pp. 163-165.

[ 2003 ]

A. Naeemi, J. A. Davis, and J. D. Meindl, “Compact physical models for the worst case crosstalk induced by near and far aggressors in a SoC,” IEEE Intl. ASIC/SOC Conf., Sept. 2003, pp. 199-202.

A. Naeemi, A. V. Mulé, and J. D. Meindl, “Partition length between board-level electrical and optical interconnects,” IEEE Intl. Interconnect Technology Conf., June 2003, pp. 230-232.

[ 2002 ]

A. Naeemi, J. A. Davis, and J. D. Meindl, “Optimal global interconnecting devices for GSI,” IEEE Int. Electron Device Meeting, December 2002, pp. 319-322.

V. Mulé, A. Naeemi, E.N. Glytsis, T. K. Gaylord, and J. D. Meindl, “Towards a comparison between chip-level optical interconnection and board-level interconnection,” IEEE Intl. Interconnect Technology Conf., June 2002, pp. 92-94.

A. Naeemi, R. Venkatesan, and J. D. Meindl, “System-on-a-chip global interconnect optimization,” Proc. ASIC/SoC Conf., September 2002, pp. 399-403.

[ 2001 ]

J. D. Meindl, R. Venkatesan, J. A. Davis, J. Joyner, A. Naeemi, P. Zarkesh-Ha, M. Bakir, T. Mulé, P. A. Kohl, and K.P. Martin, “Interconnecting device opportunities for gigascale integration (GSI),” IEEE Int. Electron Device Meeting, Dec. 2001, pp. 23.1.1 - 23.1.4.

A. Naeemi, J. A. Davis, and J. D. Meindl, “Analytical models for coupled distributed RLC lines with ideal and non-ideal return paths,” IEEE Int. Electron Device Meeting, December 2001, pp. 689-692.

A. Naeemi and J. D. Meindl, “An optimal partition between on-chip and on-board interconnects,” IEEE Intl. Interconnect Technology Conf., June 2001, pp. 131-133.

A. Naeemi, C. S. Patel, M. S. Bakir, P. Zarkesh-Ha, K. P. Martin and J. D. Meindl, “Sea of Leads: A disruptive paradigm for a system-on-a-chip (SoC),” IEEE Int. Solid State Circuits Conf., February 2001, pp. 280-281.

[ 2000 ]

A. Naeemi, P. Zarkesh-Ha, C. S. Patel, and James D. Meindl, “Performance improvement using on-board wires for on-chip interconnects,” IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging, October 2000, pp. 325-328.