Invited Presentations

[ 2016 ]

A. Naeemi, “TFETs, NCFETs, HyperFETs, SpinFETs, or MOSFETs forever?” Panel Discussion at Device Research Conference, Newark, DE, June 2016.

A. Naeemi, “Interconnect design for conventional and emerging charge based devices,” Int. Interconnect Technology Conference, San Jose, CA, May 2016.

A. Naeemi, “Spin-based interconnect technology and design,” Int. Interconnect Technology Conference, San Jose, CA, May 2016.

[ 2015 ]

A. Naeemi, “Is there a potential for a revolution in on-chip interconnect?” Panel Discussion at Int. Electron Device Meeting (IEDM), Washington DC, Dec. 2015.

A. Naeemi, “Non-volatile clocked spin wave interconnect for beyond-CMOS nanomagnet pipelines,” IMEC Workshop on Beyond-CMOS, Leuven, Belgium, Oct. 2015.

A. Naeemi, “Performance modeling for conventional and emerging interconnect technologies for CMOS and beyond-CMOS circuits,” Applied Materials Emerging Technologies Conference, Aug. 2015, Monterey, CA.

A. Naeemi, “Interconnects for emerging 'beyond CMOS' devices and circuits,” Semiconductor Technology Symp., SEMICON WEST, San Francisco, CA, July 2015.

A. Naeemi, “CMOS circuit impact of interconnects – Cu and beyond,” Semiconductor Technology Symp., SEMICON WEST, San Francisco, CA, July 2015.

V. Kumar, S. Rakheka and A. Naeemi, “High frequency models for multlayer graphene interconnects,” IEEE International Microwave Symposium, Phoenix, AZ, May 2015.

[ 2014 ]

A. Naeemi, “Performance modeling for beyond-CMOS devices and interconnects,” IMEC Workshop on Beyond-CMOS, Leuven, Belgium, Oct. 2014.

A. Naeemi, “SPICE models for metallic all-spin-logic devices and interconnects,” 72nd Annual Device Research Conference (DRC), Santa Barbra, CA, July 2014.

[ 2012 ]

S. Rakheja, A. Ceyhan, and A. Naeemi, “Interconnects for Post-CMOS switches,” CMOS Emerging Technologies Conference, Vancouver, BC, Canada, July 2012.

[ 2011 ]

A. Naeemi, “Ultra low power interconnects for nanoelectronics”, Nanoelectronics Devices for Defense and Security Conference, Brooklyn, NY, Aug. 2011.

A. Naeemi and S. Rakheja, “Interconnects for post-CMOS nanoelectronics,” DARPA sponsored Information Science and Technology (ISAT) Workshop on “Beyond Moore’s Law Cliff," San Francisco, CA, Feb. 2011.

[ 2010 ]

A. Naeemi, “Interconnect networks in 2D and 3D nanoelectronic systems,” IEEE/ACM Workshop on Variability Modeling and Characterization, San Jose, CA, Nov. 2010.

A. Naeemi, “High-frequency circuit models for carbon nanotubes and graphene nanoribbon interconnects,” IEEE Int. Microwave Symp., Workshop on New Microwave Materials and Devices Based on Nanotechnology, Anaheim, CA, May 2010.

A. Naeemi, “Communication of novel computational state variables: physical limits and circuit implications,” Int. Technology Roadmap for Semiconductors (ITRS) Teleseminar, Jan. 2010.

[ 2009 ]

A. Naeemi, “Communication of novel computational state variables: physical limits and circuit implications,” One-Day Workshop on Architectures for Post-CMOS Switches (Sponsored by SRC Nanoelectronics Research Initiative and National Science Foundation), Notre Dame, IN, Aug. 2009.

A. Naeemi, “Carbon-Based Interconnects for Nanoelectronics,” China Semiconductor Technology International Conference (Co-sponsored by IEEE Electron Devices Society and China Electronics Materials Industry Association), Shanghai, China, March 2009.

[ 2008 ]

A. Naeemi, “Carbon-Based Interconnects for Nanoelectronics,” VLSI/ULSI Multilevel Interconnection Conference, State-of-the-Art Seminar, Fremont, CA, Oct. 2008.

A. Naeemi, “Carbon Nanotube and Graphene Nanoribbon Interconnects,” IEEE Int. Sym. Electromagnetic Compatibility, Detroit, MI, Sept. 2008.

A. Naeemi, “Carbon Nanotube and Graphene Nanoribbon Interconnects,” IEEE ITHERM, Orlando, FL, May 2008.

[ 2007 ]

A. Naeemi, “Low power carbon nanotube and graphene nanoribbon interconnects,” FCRP IFC/MSD Workshop on Power Efficient Devices and Interconnects, Massachusetts Institute of Technology, Cambridge, MA, March 2007.

A. Naeemi, “Carbon nanotube interconnect modeling,” Topical Workshop On Carbon Nanotubes: Materials, Devices, Modeling, and Circuits, Massachusetts Institute of Technology, Cambridge, MA, March 2007.

[ 2006 ]

A. Naeemi, “Design challenges for nanotechnology-based nanoelectronics,” Panel Discussion at IEEE/ICST Nano Networks Workshop, Lausanne, Switzerland, Sept. 2006.

A. Naeemi, “Performance modeling for metallic single wall carbon nanotube interconnects for gigascale integration (GSI),” 135th TMS Annual Meeting and Exhibition, San Antonio, TX, May 2006.

[ 2005 ]

A. Naeemi, “Performance modeling for copper and carbon nanotube interconnects for gigascale integration,” Semiconductor Research Corporation (SRC) E-Workshop, Dec. 2005.

A. Naeemi, “The challenges interconnect technologies face at the 45nm technology node and beyond,” Panel Discussion at Sematech/Novellus Workshop on Copper Resistivity, Burlingame, CA, June 2005.

A. Naeemi, “Physical limits and potential nanotechnology solutions for GSI multi-level interconnect networks; a quantitative analysis,” Sematech/Novellus Workshop on Copper Resistivity, Burlingame, CA, June 2005.

[ 2003 ]

A. Naeemi, “Future of computing and communication technologies and applications,” Panel Discussion at IEEE All-Day Workshop on Devices, Interconnects, and Packaging for Next Generation Computing and Communication Applications, Arizona State University, Tempe, AZ, Nov. 2003.

A. Naeemi, “Optimal global interconnects for gigascale integration,” IEEE All-Day Workshop on Devices, Interconnects, and Packaging for Next Generation Computing and Communication Applications, Arizona State University, Tempe, AZ, Nov. 2003.