Instructor: Azad Naeemi

Class: Van Leer E261

Semester: Spring 2015

M-W 2-3 p.m.

The purpose of this course is to provide graduate and senior level undergraduate students in electrical, computer, materials and chemical engineering as well as computer science and physics with a **fundamental understanding of the key laws of physics** that will govern future opportunities to achieve multi-billion to multi-trillion transistor microprocessors, logic and memory chips or XXI century gigascale integration (GSI).

The most important economic event of the XX century was the advent of the information revolution. The principal driving force of that revolution is the silicon microchip. Since its inception in 1959, the productivity of microchip technology has improved by eight decades and chip performance has improved by six decades! These sustained exponential rates of advance are unmatched in technological history.

Opportunities for integrating many billions of transistors in a single silicon chip are governed by a hierarchy of physical limits whose five levels are codified as: 1) fundamental, 2) material, 3) device, 4) circuit and 5) system. The three key fundamental limits are derived from thermodynamics, quantum mechanics and electromagnetics. Semiconductors impose three critical material limits described by the amount of energy storage required to support a binary switching transition, carrier transit time during the transition and the heat removal capacity of the generic device structure implementing the transition. However, since future information processing elements may potentially use materials other than semiconductors, new material limits may emerge in the future. Interconnect materials impose other critical material limits. The four most important device limits are imposed by the switching energy and delay of a transistor and the response time and cross talk of interconnects. The static transfer curve, switching energy and propagation delay time of a binary logic circuit are three inescapable generic circuit limits and the response time of a global interconnect circuit is the final critical circuit limit. System limits are the most numerous, most nebulous and most restrictive limits of the hierarchy. The architecture of a system-on-a-chip, the switching energy of its critical path circuits, the heat removal capacity of its packaging, its clock frequency and its spatial dimensions are critical system limits that determine the design space for each new product generation.

The final grade will be calculated as follows:

- Homework 30%
- Class participation 10%
- Two Class Quizzes 20%
- Term Paper 20%

The term paper in this course is in lieu of a final exam.

By late March, you are expected to have chosen a specific topic to write a term paper on it. You are required to submit a half page abstract on March 29. Original ideas on the limits at fundamental, material, device, circuit, or system levels are strongly encouraged and will result in bonus credit. You can focus on an emerging material, device, circuit, or system concept, or you can work on limits and opportunities for more evolutionary material, device, circuit, or system paradigms. The goal of this project is to use the course material and your creativity to make an original contribution not writing term papers that are pure literature surveys.

Weeks 1: Course Overview and Introduction to Hierarchy of Limits

Week 2: Fundamental Limits: Laws of thermodynamics, Uncertainty Principle

Week 3 & 4: Fundamental Limits: Electromagnetism, Quantum resistance, Quantum capacitance, Kinetic inductance

Week 5: Material Limits: Semiconductors, Insulators, and metals

Week 6: Material Limits: Carbon Nanotubes and Graphene

Week 7: Device Limits: Planar Si MOSFETs, FinFETs

Week 8: Device Limits: Ballistic Transistors, Carbon Nanotube FETs, Tunnel FETs

Week 9: Device Limits: Tunnel FETs

Week 10: Circuit Limits: static transfer curve, switching energy and propagation delay time of a binary logic circuit

Week 11: Circuit Limits: Fault and defect tolerant circuit design

Week 12: System Limits: Critical Path Delay, Power Density and Heat removal

Week 13: System Limits: On-Chip and Off-Chip Bandwidth

Weeks 14-15: Computation Using Novel State Variables

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